Description

This page is still under construction.

An EROS address space is made up of a tree of nodes whose leaves are pages. Pages may contain data or capabilities (but not both), according to the type of the page.

To understand virtual address translation, it is useful to think of an address as made up of a virtual page address and a page offset:

+----------------------+-------------+
| Virtual Page Address | Page Offset |
+----------------------+-------------+
	  

Both the size of the page offset portion of the address and the size of the complete virtual address are dictated by the underlying hardware.

When a program references a memory address, the virtual page address is interpreted by traversing the address space until the appropriate page is found. The page offset is then used to reference the appropriate object (byte, halfword, word, doubleword, quadword, or capability) within the page.

Because address space and node capabilities encode the size of their subspace, the algorithm for traversing the address space tree is slightly more complicated than the comparable hardware mechanism on most processors. The 68881 MMU uses a fairly similar approach.

Address Translation

Translation of an address begins by examining the key in the address space slot of the process. In traversing an address space, a sequence of keys is examined in turn. The action taken depends on:

1. The type of the key,

2. The size of the address space named by that key,

3. The current offset relative to the start of the segment named by that key.

Sizes are measured in terms of log space size. To compute the log space size of a subspace, first determine how many pages that subspace holds. The log space size is then ciel(log_ndsz(npages)), where ndsz is the number of slots in a node. Thus, on a 32-bit address machine with 4096 byte pages and 32 slot nodes, the lss values usually associated with address translation are as follows:

lss	Size in pages
0	1
1	2..32
2	33..1,024
3	1,025..32,768
4	32,769..1,048,576