Origin of some Keykos ideas
Wed, 23 Nov 94 10:10:50 -0500
One exception to this, I think, is the cache design on the RS/6000
which I have heard had some sort of mode that supported transaction
abort by keeping updates in cache until the transaction
completed. I don't know the entire design.
The RS/6000 MMU provided hardware-implemented locking of main memory
at the granularity of a cache line. To the best of my knowledge, the
cache did not provide features specific to transaction abort.
As it turned out, the transaction support was broken, and was removed
in subsequent chip revisions.