[eros-cvs] cvs commit: eros/src/base/sys/kernel kern_Check.cxx kern_Segment.cxx
shap@eros.cs.jhu.edu
shap@eros.cs.jhu.edu
Sun, 1 Apr 2001 15:18:55 -0400
shap 01/04/01 15:18:55
Modified: src/base/sys/arch/i486/arch-kerninc PTE.hxx
src/base/sys/arch/i486/kernel Machine.cxx PageFault.cxx
UserContextIPC.cxx UserContextInvoke.cxx
src/base/sys/ddb db_eros.cxx
src/base/sys/kernel kern_Check.cxx kern_Segment.cxx
Log:
Rename PTE_DV to PTE_V per cap page removal
Revision Changes Path
1.7 +4 -2 eros/src/base/sys/arch/i486/arch-kerninc/PTE.hxx
Index: PTE.hxx
===================================================================
RCS file: /cvs/eros/src/base/sys/arch/i486/arch-kerninc/PTE.hxx,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -r1.6 -r1.7
--- PTE.hxx 2001/03/13 03:06:07 1.6
+++ PTE.hxx 2001/04/01 19:18:54 1.7
@@ -24,7 +24,7 @@
#define __U(x) (x##u)
#endif
-#define PTE_DV __U(0x001) /* valid for data (Intel: 'present') */
+#define PTE_V __U(0x001) /* valid (Intel: 'present') */
#define PTE_W __U(0x002) /* writable */
#define PTE_USER __U(0x004) /* user-accessable page */
#define PTE_WT __U(0x008) /* write through */
@@ -40,6 +40,8 @@
#define PTE_FRAMEBITS __U(0xfffff000)
#define PTE_INFOBITS __U(0x00000fff)
+#define PTE_ZAPPED __U(0x0)
+
#ifndef __ASSEMBLER__
/* This file requires #include <kerninc/kernel.hxx> (for assert) */
@@ -64,7 +66,7 @@
void Invalidate()
{
- w_value = 0;
+ w_value = PTE_ZAPPED;
PteZapped = true;
}
1.111 +9 -9 eros/src/base/sys/arch/i486/kernel/Machine.cxx
Index: Machine.cxx
===================================================================
RCS file: /cvs/eros/src/base/sys/arch/i486/kernel/Machine.cxx,v
retrieving revision 1.110
retrieving revision 1.111
diff -u -r1.110 -r1.111
--- Machine.cxx 2001/03/05 05:22:01 1.110
+++ Machine.cxx 2001/04/01 19:18:54 1.111
@@ -291,7 +291,7 @@
for (uint32_t i = 0; i < nFrames; i++) {
PTE_SET(pageDir[dirndx], (VTOP(pageTab) & PTE_FRAMEBITS) );
- PTE_SET(pageDir[dirndx], PTE_W|PTE_DV|PTE_ACC|PTE_USER);
+ PTE_SET(pageDir[dirndx], PTE_W|PTE_V|PTE_ACC|PTE_USER);
pageTab += NPTE_PER_PAGE;
dirndx++;
@@ -388,7 +388,7 @@
assert (tabndx == 0);
/* Pentium or higher. Use large pages: */
PTE_SET(pageDir[dirndx], (paddr & PTE_FRAMEBITS) );
- PTE_SET(pageDir[dirndx], PTE_W|PTE_DV|PTE_PGSZ|globalPage);
+ PTE_SET(pageDir[dirndx], PTE_W|PTE_V|PTE_PGSZ|globalPage);
#ifdef WRITE_THROUGH
PTE_SET(pageDir[dirndx], PTE_WT);
#endif
@@ -415,14 +415,14 @@
#endif
PTE_SET(pageDir[dirndx], (VTOP(pageTab) & PTE_FRAMEBITS) );
- PTE_SET(pageDir[dirndx], PTE_W|PTE_DV|globalPage);
+ PTE_SET(pageDir[dirndx], PTE_W|PTE_V|globalPage);
pageDir[pdirndx] = pageDir[dirndx];
}
assert((paddr & EROS_PAGE_MASK) == 0);
PTE_SET(pageTab[tabndx], (paddr & PTE_FRAMEBITS) );
- PTE_SET(pageTab[tabndx], PTE_DV|globalPage);
+ PTE_SET(pageTab[tabndx], PTE_V|globalPage);
/* Note that the processor won't honor the writable bit in
* supervisor mode, so there really isn't any point to setting it.
@@ -442,7 +442,7 @@
* we load the new mapping table pointer:
*/
if (vaddr == 0)
- PTE_CLR(pageTab[tabndx], PTE_W|PTE_DV);
+ PTE_CLR(pageTab[tabndx], PTE_W|PTE_V);
}
}
@@ -468,7 +468,7 @@
situation, and if we really needed to copy the PTEs were weren't
going to see and TLB locality in any case. */
PTE_SET(pageDir[KVTOL(KVA_PTEBUF) >> 22], (VTOP(pageTab) & PTE_FRAMEBITS) );
- PTE_SET(pageDir[KVTOL(KVA_PTEBUF) >> 22], PTE_W|PTE_DV );
+ PTE_SET(pageDir[KVTOL(KVA_PTEBUF) >> 22], PTE_W|PTE_V );
/* Following is harmless on pre-pentium: */
PTE_CLR(pageDir[KVTOL(KVA_PTEBUF) >> 22], PTE_PGSZ );
@@ -479,7 +479,7 @@
/* 64K message limit = 16 pages + 1 for unaligned. */
for (int j = 0; j < 17; j++) {
- PTE_SET(*pte, PTE_W|PTE_DV|PTE_DRTY|PTE_ACC);
+ PTE_SET(*pte, PTE_W|PTE_V|PTE_DRTY|PTE_ACC);
#ifdef WRITE_THROUGH
if (cpuType >= 5)
@@ -632,10 +632,10 @@
pte++;
if (p1) {
(*pte) = p1;
- PTE_SET(*pte, PTE_DV);
+ PTE_SET(*pte, PTE_V);
}
else
- PTE_CLR(*pte, PTE_DV);
+ PTE_CLR(*pte, PTE_V);
if (CpuType > 3) {
Machine::FlushTLB(KVTOL(va));
1.164 +7 -258 eros/src/base/sys/arch/i486/kernel/PageFault.cxx
Index: PageFault.cxx
===================================================================
RCS file: /cvs/eros/src/base/sys/arch/i486/kernel/PageFault.cxx,v
retrieving revision 1.163
retrieving revision 1.164
diff -u -r1.163 -r1.164
--- PageFault.cxx 2001/03/05 05:22:01 1.163
+++ PageFault.cxx 2001/04/01 19:18:54 1.164
@@ -108,7 +108,7 @@
#define ADDATTR(s) do { const char *sp = (s); *nxtAttr++ = ','; while (*sp) *nxtAttr++ = *sp++; } while (0)
- if (PTE_ISNOT(*this, PTE_DV)) *nxtAttr++ = '!';
+ if (PTE_ISNOT(*this, PTE_V)) *nxtAttr++ = '!';
*nxtAttr++ = 'D';
*nxtAttr++ = 'V';
@@ -347,7 +347,7 @@
}
-#define DATA_PAGE_FLAGS (PTE_ACC|PTE_USER|PTE_DV)
+#define DATA_PAGE_FLAGS (PTE_ACC|PTE_USER|PTE_V)
#ifdef SMALL_SPACES
bool
@@ -443,7 +443,7 @@
bool needInvalidate = false;
- if (isWrite && PTE_IS(thePTE, PTE_DV)) {
+ if (isWrite && PTE_IS(thePTE, PTE_V)) {
/* We are doing this because the old PTE had insufficient
* permission, so we must zap the TLB.
*/
@@ -509,7 +509,6 @@
* of this is an issue for local windows,
*/
-#if 1
inline uint64_t
BLSS_MASK64(uint32_t blss)
{
@@ -624,7 +623,7 @@
uint32_t pdeNdx = (la >> 22) & 0x3ffu;
PTE& thePDE = pTable[pdeNdx];
- if ( PTE_IS(thePDE, PTE_DV|PTE_USER) ) {
+ if ( PTE_IS(thePDE, PTE_V|PTE_USER) ) {
/* We could short-circuit the walk in this case by remembering
* the status of /wi.canWrite/ in a spare bit in the PTE, but
@@ -755,7 +754,7 @@
* See if we need to build a new page table:
*/
- if (PTE_IS(thePDE, PTE_DV)) {
+ if (PTE_IS(thePDE, PTE_V)) {
pTable = (PTE *) PTOV(thePDE.PageFrame());
if (wi.canWrite && !PTE_IS(thePDE, PTE_W)) {
@@ -793,7 +792,7 @@
*/
PTE_SET(thePDE, (VTOP((kva_t)pTable) & PTE_FRAMEBITS));
- PTE_SET(thePDE, PTE_ACC|PTE_USER|PTE_DV);
+ PTE_SET(thePDE, PTE_ACC|PTE_USER|PTE_V);
/* Using /canWrite/ instead of /isWrite/ reduces the number of
* cases in which we need to rebuild the PDE without altering the
@@ -845,7 +844,7 @@
assert ((pageAddr & EROS_PAGE_MASK) == 0);
assert (pageAddr < (kpa_t) start || pageAddr >= (kpa_t) end);
- if (isWrite && PTE_IS(thePTE, PTE_DV)) {
+ if (isWrite && PTE_IS(thePTE, PTE_V)) {
/* We are doing this because the old PTE had insufficient
* permission, so we must zap the TLB.
*/
@@ -891,256 +890,6 @@
return false;
}
-#else
-bool
-proc_DoPageFault(Process * p, ula_t la, bool isWrite, bool prompt)
-{
-#ifdef DBG_WILD_PTR
- if (dbg_wild_ptr)
- Check::Consistency("Top of DoPageFault()");
-#endif
-
- DoPageFault_CallCounter++;
-
- DEBUG(pgflt) {
- MsgLog::printf("DoPageFault: ctxt=0x%08x EIP 0x%08x la=0x%08x, isWrite=%c prompt=%c\n",
- p,
- p->fixRegs.EIP,
- la,
- isWrite ? 't' : 'f',
- prompt ? 't' : 'f');
- }
-
-#ifdef SMALL_SPACES
- uva_t va = la - p->bias;
-#else
- uva_t va = la;
-#endif
-
- /* If LA is simply out of range, then forget the whole thing: */
- if ( la >= KVA ) {
- MsgLog::dprintf(true, "Domain accessed kernel or small space la\n");
- p->SetFault(FC_DataInvalidAddr, va);
- return false;
- }
-
-#ifdef SMALL_SPACES
- if (p->smallPTE)
- return proc_DoSmallPageFault(p, la, isWrite, prompt);
-#endif
-
- /* If LA is simply out of range, then forget the whole thing: */
- if ( la >= UMSGTOP ) {
- MsgLog::dprintf(true, "Large domain accessed small space la\n");
- p->SetFault(FC_DataInvalidAddr, va);
- return false;
- }
-
- /* If we discover on the way to load the process that it's mapping
- * table register was voided, we substituted KERNPAGEDIR. Notice
- * that here:
- */
- if ( p->fixRegs.MappingTable == KERNPAGEDIR )
- p->fixRegs.MappingTable = 0;
-
- /* Set up a WalkInfo structure and start building the necessary
- * mapping table, PDE, and PTE entries.
- */
-
- SegWalkInfo wi;
- wi.vaddr = va;
- wi.segObj = 0;
- wi.writeAccess = isWrite;
- wi.prompt = prompt;
-
-#if EROS_NODE_SIZE == 16
- const walk_root_blss = 7;
- const walk_top_blss = 5;
- const walk_mid_blss = 4;
-#elif EROS_NODE_SIZE == 32
- const walk_root_blss = 6;
- const walk_top_blss = 4;
-#else
-#error "Unhandled BLSS value in DoPageFault()."
-#endif
-
- /* Begin the traversal... */
- if ( !proc_WalkSeg(p, wi, walk_root_blss,
- (PTE *)&p->fixRegs.MappingTable, 0, false) ) {
- p->SetFault(wi.segFault, va);
- return false;
- }
-
- if (p->fixRegs.MappingTable == 0) {
- /* See if a mapping table has already been built for this address
- * space. If so, just use it. Using wi.segBlss is okay here
- * because the mapping table pointer will be zapped if anything
- * above this point gets changes, whereupon the gunk the the page
- * directory will no longer matter.
- */
- ObjectHeader *pTable;
-
- {
- ObjectHeader *pObjHdr = wi.segObj;
-
- pTable =
- pObjHdr->FindProduct(wi, EROS_NODE_LGSIZE /* ndx */, isWrite);
- }
-
- bool newTable = false;
- if (pTable == 0) {
- pTable = proc_MakeNewPageDirectory(wi, isWrite);
- newTable = true;
- }
-
- kva_t tableAddr = ObjectCache::ObHdrToPage(pTable);
-
- p->fixRegs.MappingTable = VTOP(tableAddr);
- }
-
-
- /* Start building the PDE entry: */
- uint32_t pdeNdx = (la >> 22) & 0x3ffu;
- PTE& thePDE = ((PTE*) PTOV(p->fixRegs.MappingTable) )[pdeNdx];
-
- /* Translate the top 8 (10) bits of the address: */
- if ( !proc_WalkSeg(p, wi, walk_top_blss, &thePDE, 0, true) )
- return false;
-
- /* If we get this far, we need the page table to proceed further.
- * See if we need to build a new page table:
- */
-
- bool needInvalidate = false;
-
- if ( PTE_ISNOT(thePDE, PTE_DV) || (PTE_ISNOT(thePDE,PTE_W) && isWrite) ) {
- uint32_t productNdx = 0;
-
- if (PTE_IS(thePDE, PTE_DV)) {
- /* We are doing this because the old PDE had insufficient
- * permission, so we must zap the TLB.
- */
- needInvalidate = true;
- }
-
-#if EROS_NODE_SIZE == 16
- /* If we actually ended up at a BLSS=5 node, that node produces 4
- * distinct page tables, and we must now find the proper one.
- * Permissions below the BLSS::bit24 layer will be managed within
- * the page tables, so we do not worry about those here. It is
- * possible that we ended up at something smaller than a
- * BLSS::bit24 node, in which case only one page table is
- * produced. Note that the productNdx computation will in that
- * case generate '0', which is precisely what we want.
- */
-
- if (wi.segBlss == walk_top_blss)
- productNdx = (la >> 22) & 0x3;
-#endif
-
- /* Level 0 product need never be a read-only product. We use
- * the write permission bit at the PDE level.
- */
-
- ObjectHeader *pTable;
-
- {
- ObjectHeader *pObjHdr = wi.segObj;
-
- pTable =
- pObjHdr->FindProduct(wi, productNdx, true);
- }
-
- if (pTable == 0)
- pTable = proc_MakeNewPageTable(wi, productNdx);
-
- PTE *tableAddr = (PTE *) ObjectCache::ObHdrToPage(pTable);
-
- /* The level 0 page table is still contentless - there is no
- * need to build depend table entries covering it's contents.
- * We simply need to fill in the page directory entry:
- */
-
- thePDE.Invalidate();
- PTE_SET(thePDE, (VTOP((kva_t)tableAddr) & PTE_FRAMEBITS));
- PTE_SET(thePDE, PTE_ACC|PTE_USER|PTE_DV);
- }
-
- uint32_t pteNdx = (la >> 12) & 0x3ffu;
- kpa_t physPageTableAddr = thePDE.PageFrame();
-
- PTE* pageTable = (PTE*) PTOV(physPageTableAddr);
- PTE& thePTE = pageTable[pteNdx];
-
-#if EROS_NODE_SIZE == 16
- /* Translate the next 4 bits of the address, after which we will
- * have translated the top 10 bits of the LA, and can set the
- * Writable bit of the PDE accordingly if this is a write request.
- */
-
- if ( !proc_WalkSeg(p, wi, walk_mid_blss, &thePDE, &thePTE) )
- return false;
-#endif
-
- /* Translate the remaining bits of the address: */
- if ( !proc_WalkSeg(p, wi, EROS_PAGE_BLSS, &thePTE, 0, true) )
- return false;
-
- assert(wi.segObj);
- assert(wi.segObj->obType == ObType::PtCapPage ||
- wi.segObj->obType == ObType::PtDataPage);
-
- if (isWrite)
- PTE_SET(thePDE, PTE_W);
-
- kpa_t pageAddr = 0;
-
- ObjectHeader *pPageHdr = wi.segObj;
-
- if (isWrite)
- pPageHdr->MakeObjectDirty();
-
- pageAddr = VTOP(ObjectCache::ObHdrToPage(pPageHdr));
-
- if (pageAddr == 0)
- MsgLog::dprintf(true, "pPageHdr 0x%08x at addr 0x%08x!! (wi=0x%08x)\n",
- pPageHdr, pageAddr, &wi);
-
- assert ((pageAddr & EROS_PAGE_MASK) == 0);
- assert (pageAddr < (kpa_t) start || pageAddr >= (kpa_t) end);
-
- if (isWrite && PTE_IS(thePTE, PTE_DV)) {
- /* We are doing this because the old PTE had insufficient
- * permission, so we must zap the TLB.
- */
- needInvalidate = true;
- }
-
- thePTE.Invalidate();
- PTE_SET(thePTE, (pageAddr & PTE_FRAMEBITS) );
- PTE_SET(thePTE, DATA_PAGE_FLAGS);
- if (isWrite)
- PTE_SET(thePTE, PTE_W);
-#ifdef WRITE_THROUGH
- if (CpuType >= 5)
- PTE_SET(thePTE, PTE_W);
-#endif
-
- /* If cap page, better not be data valid. */
- assert ( (wi.segObj->obType != ObType::PtCapPage) ||
- (PTE_IS(thePTE, PTE_DV) == false) );
-
- if (needInvalidate)
- Machine::FlushTLB(la);
-
-#ifdef DBG_WILD_PTR
- if (dbg_wild_ptr)
- Check::Consistency("End of DoPageFault()");
-#endif
-
- return true;
-}
-#endif
static ObjectHeader*
proc_MakeNewPageDirectory(SegWalkInfo& wi)
1.46 +1 -1 eros/src/base/sys/arch/i486/kernel/UserContextIPC.cxx
Index: UserContextIPC.cxx
===================================================================
RCS file: /cvs/eros/src/base/sys/arch/i486/kernel/UserContextIPC.cxx,v
retrieving revision 1.45
retrieving revision 1.46
diff -u -r1.45 -r1.46
--- UserContextIPC.cxx 2001/03/05 05:22:01 1.45
+++ UserContextIPC.cxx 2001/04/01 19:18:54 1.46
@@ -162,7 +162,7 @@
if (proc_DoPageFault(p, ula, writeAccess, prompt) == false)
return 0;
- PTE* pte = proc_TranslatePage(p, ula, PTE_DV|PTE_USER, writeAccess);
+ PTE* pte = proc_TranslatePage(p, ula, PTE_V|PTE_USER, writeAccess);
#if 0
MsgLog::dprintf(true, "Resulting PTE* is 0x%08x\n", pte);
#endif
1.85 +3 -3 eros/src/base/sys/arch/i486/kernel/UserContextInvoke.cxx
Index: UserContextInvoke.cxx
===================================================================
RCS file: /cvs/eros/src/base/sys/arch/i486/kernel/UserContextInvoke.cxx,v
retrieving revision 1.84
retrieving revision 1.85
diff -u -r1.84 -r1.85
--- UserContextInvoke.cxx 2001/01/08 20:57:50 1.84
+++ UserContextInvoke.cxx 2001/04/01 19:18:54 1.85
@@ -50,7 +50,7 @@
ula &= ~EROS_PAGE_MASK;
while (ula < ulaTop) {
- PTE *pte0 = proc_TranslatePage(this, ula, PTE_DV|PTE_USER, false);
+ PTE *pte0 = proc_TranslatePage(this, ula, PTE_V|PTE_USER, false);
if (pte0 == 0)
pte0 = proc_BuildMapping(this, ula, false, false);
@@ -102,7 +102,7 @@
ula &= ~EROS_PAGE_MASK;
while (ula < ulaTop) {
- PTE *pte0 = proc_TranslatePage(this, ula, PTE_DV|PTE_USER, true);
+ PTE *pte0 = proc_TranslatePage(this, ula, PTE_V|PTE_USER, true);
if (pte0 == 0)
pte0 = proc_BuildMapping(this, ula, true, true);
@@ -149,7 +149,7 @@
ula &= ~EROS_PAGE_MASK;
while (ula < ulaTop) {
- PTE *pte0 = proc_TranslatePage(this, ula, PTE_DV|PTE_USER, true);
+ PTE *pte0 = proc_TranslatePage(this, ula, PTE_V|PTE_USER, true);
if (pte0 == 0)
pte0 = proc_BuildMapping(this, ula, true, false);
1.135 +1 -1 eros/src/base/sys/ddb/db_eros.cxx
Index: db_eros.cxx
===================================================================
RCS file: /cvs/eros/src/base/sys/ddb/db_eros.cxx,v
retrieving revision 1.134
retrieving revision 1.135
diff -u -r1.134 -r1.135
--- db_eros.cxx 2001/02/26 07:49:01 1.134
+++ db_eros.cxx 2001/04/01 19:18:54 1.135
@@ -1701,7 +1701,7 @@
PTE* pde = space + hi;
pte_print(base, "PDE", pde);
- if (PTE_ISNOT(*pde, PTE_DV))
+ if (PTE_ISNOT(*pde, PTE_V))
db_printf("0x%08x PTE <invalid>\n", base);
else {
PTE *pte = (PTE *) pde->PageFrame();
1.27 +1 -1 eros/src/base/sys/kernel/kern_Check.cxx
Index: kern_Check.cxx
===================================================================
RCS file: /cvs/eros/src/base/sys/kernel/kern_Check.cxx,v
retrieving revision 1.26
retrieving revision 1.27
diff -u -r1.26 -r1.27
--- kern_Check.cxx 2001/01/08 20:57:51 1.26
+++ kern_Check.cxx 2001/04/01 19:18:55 1.27
@@ -199,7 +199,7 @@
for (uint32_t ent = 0; ent < MAPPING_ENTRIES_PER_PAGE; ent++) {
PTE& thePTE = pte[ent];
- if (PTE_IS(thePTE, PTE_DV|PTE_W)) {
+ if (PTE_IS(thePTE, PTE_V|PTE_W)) {
uint32_t pageFrame = thePTE.PageFrame();
kva_t thePage = PTOV(pageFrame);
1.2 +0 -19 eros/src/base/sys/kernel/kern_Segment.cxx
Index: kern_Segment.cxx
===================================================================
RCS file: /cvs/eros/src/base/sys/kernel/kern_Segment.cxx,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -r1.1 -r1.2
--- kern_Segment.cxx 2001/02/24 03:00:27 1.1
+++ kern_Segment.cxx 2001/04/01 19:18:55 1.2
@@ -29,22 +29,12 @@
/* Extracted as macro for clarity of code below, which is already too
* complicated.
- * Merge must be prohibited on mapping root entries, since merging
- * those breaks the context cache.
*/
-#if 1
#define ADD_DEPEND(pKey) \
assert (pPTE0); \
Depend_AddKey(pKey, pPTE0, canMerge); \
if (pPTE1) \
Depend_AddKey(pKey, pPTE1, canMerge);
-#else
-#define ADD_DEPEND(pKey) \
- assert (pPTE0); \
- Depend_AddKey(pKey, pPTE0, (pPTE0 == mappingRoot)?false:true); \
- if (pPTE1) \
- Depend_AddKey(pKey, pPTE1, true);
-#endif
/* proc_WalkSeg() is a performance-critical path. The segment walk
logic is complex, and it occurs in the middle of page faulting
@@ -453,7 +443,6 @@
* passing option turned on, so do not reuse scratchKey.
*/
-#if 1
inv.redNodeKey.InitType(KtNode);
inv.redNodeKey.SetPrepared();
wi.redSeg->TransLock();
@@ -464,14 +453,6 @@
inv.redNodeKey.ok.prev = (KeyRing*) wi.redSeg;
wi.redSeg->kr.next = (KeyRing *) &inv.redNodeKey;
inv.redNodeKey.ok.next->prev = (KeyRing*) &inv.redNodeKey;
-#else
- inv.redNodeKey.InitType(KtNode);
- inv.redNodeKey.SetUnprepared();
- inv.redNodeKey.subType = 0;
- inv.redNodeKey.keyData = BLSS::RedSeg;
- inv.redNodeKey.unprep.oid = wi.redSeg->ob.oid;
- inv.redNodeKey.unprep.count = wi.redSeg->ob.allocCount;
-#endif
inv.flags |= INV_REDNODEKEY;
keyToPass = &inv.redNodeKey;