> Provided that
>
> 1) You provide the patches under the terms of the EROS license at
> http://www.cis.upenn.edu/~eros/legal/license/EPL.html
> 2) You own the code, and are therefore authorized to donate it
Yes, I am happy to accept the license and I own the code I write.
> Since we are rapidly reaching the point where my own changes cannot be
> incorporated, I may do some round trips with you to get the patches just
> right, but I definitely welcome the help.
No problem.
> A few requests, since you seem to know the processor well enough that these
> will likely present no difficulty for you:
>
> 1. I have not had an opportunity to check the CPU Identification logic (I
> think that's in lostart.S) for the AMD K6. Could you look it over and
> verify that it is doing something plausible?
I'll take a look.
> 2. I do not know if the AMD K6 supports 4M pages. This makes a big
> difference in performance. Could you let me know if it does?
It certainly does. I didn't think it did, but the manual says it can, and can mix 4k and 4M pages in the same page directory.
> Ultimately, doing this stuff by dispatching on processor type is pretty
> stupid. What we really need is a "feature mask". I'll think about that
> and send a request to the list for input.
Agreed. Then we can simply do
if (nFeatureMask & FM_PERFCOUNTERS) {...}
> I need to touch that code tomorrow anyway, so let me put in a rudimentary
> feature mask change and then encourage (nay, BEG) you to modify it
> appropriately for the K6.
OK, let me know when it's in, and I'll do a cvs update.
> As to systrace.S, yes, inline assembly would be a definite improvement.
OK, I'll get going on that right away.
Regards,
Peter